In communication terminals such as radio terminals in which there has been a rapid increase in growth, there is incorporated an electrical circuit that includes an amplifier. When a compound FET (Field Effect Transistor) is used as the amplifier used in the electrical circuit, particularly in the power amplifier and the like, a gate bias circuit arranged on the same chip as a multi-finger FET, that acts as an amplifier body and that is made of FETs having different sizes, is used instead of a resistive divider so that characteristics are improved at the time of high output.
When a configuration using a current mirror circuit as the gate bias circuit is used, a transistor used in the power amplifier body and a transistor used in the gate bias circuit must have the same characteristics. In compound FETs, however, there may occur a deviation in threshold voltage on the same chip. Thus, the value of current flowing in the amplifier is different from the design value. Further, since these variations in threshold voltage are not uniform, there occurs a variation in the value of current flowing in the amplifier between chips.
Thus, in order to avoid such variation, there has been proposed a method of arranging current transistors regularly and thereby forming a constant current generating circuit (for example, refer to WO 1999/067884 pamphlet).
Further, there has been proposed a method of using multiple transistors having the same gate length and the same gate width and thereby suppressing variation in characteristics between transistors (for example, refer to Japanese Patent Laid-Open No. 1996-116222).
Further, there has been proposed a method of defining the order of multiple transistors and arranging them in parallel so that the characteristics of paired transistors used as transistors of a differential amplifier are made equal (refer to Japanese Patent Laid-Open No. 1992-073961 and Japanese Patent No. 1996-008264).
However, with the method described in WO 1999/067884 pamphlet, the outer circumference of transistors arranged regularly in a shape of Sea of Gate (SOG) has great variation due to loading effects or the like.
The method described in Japanese Patent Laid-Open No. 1996-116222 does not describe the arrangement and layout of the transistors. Also, there is no description of a case where the number of transistors is one.
In the methods described in Japanese Patent Laid-Open No. 1992-073961 and Japanese Patent No. 1996-008264, a configuration for making the sizes of paired transistors equal is also needed; this configuration is not needed for constituting the present invention.